1. Field of the Invention
The present invention relates to an apparatus and method for attaching a semiconductor die to a lead frame. More particularly, the present invention relates to use of "flip-chip" configured dice in combination with lead frames, and to relocating electric contact points of a semiconductor die, preferably a flip-chip, to "open" locations on the semiconductor die active surface to facilitate large, robust interconnection between the electric contact points and the lead frame.
2. State of the Art
Conventional lead frame design inherently limits package density for a given die size because the die-attach paddle of the lead frame must be larger than the die to which it is bonded. The larger the die, the less space that remains around the periphery of the die-bonding pad for wire bonding. Furthermore, the inner lead ends on the standard lead frame provide anchorage for the leads when the leads and the die are encapsulated in plastic. Therefore, as the die size is increased in relation to a given package size, there is a corresponding reduction in the space (depth) along the sides of the package for the encapsulating plastic which joins the top and bottom of the plastic body at the mold part line and anchors the leads. Thus, as the leads and encapsulant are subjected to the normal stresses of subsequent trimming, forming and assembly operations, the encapsulating plastic may crack, compromising package integrity and substantially increasing the probability of premature device failure.
One method of chip attachment which permits a larger die to be accommodated in a plastic package size originally developed for a smaller die is a so-called "lead-over-chip" ("LOC") arrangement. Conventional LOC devices employ a die with one or more central rows of bond pads, and have a plurality of leads which are disposed over and attached to the active surface of the semiconductor die, thus the name lead-over-chip. A "lead-under-chip" ("LUC") arrangement is substantially the same as the LOC arrangement, but with the leads extending under the semiconductor die. A primary advantage of LOC/LUC arrangements is that the ratio between the size of the semiconductor die and the size of a package which encapsulates the semiconductor die is relatively high in comparison to conventional devices employing dice with peripheral bond pads and leads terminating adjacent the die. This advantage is achieved because the semiconductor die is attached to the extended leads, and the packaging material does not merely interlock with the leads about the periphery of the package.
U.S. Pat. No. 4,862,245 issued Aug. 29, 1989 to Pashby et al. ("the '245 patent") illustrates an LOC arrangement on a semiconductor die 30. With reference to FIG. 5 herein, with such an arrangement a lead frame (periphery not shown) has a plurality of leads 36 which extends over the semiconductor die 30 toward a central or axial line of bond pads 34. A plurality of bond wires 32 makes the electrical connection between the inner ends of leads 36 and the bond pads 34. In wirebonding, the bond wires 32 are attached, one at a time, to their respective bond pads 34 on the semiconductor die 30 and extend to a corresponding lead or trace end 36 on a lead frame or printed circuit board (not shown). Bond wires as such as 32 are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding--using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding--using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding--using a combination of pressure, elevated temperature, arrangement and ultrasonic vibration bursts. Film-type alpha barriers 38 are provided between the semiconductor die 30 and the leads 36, and are adhered to both, thus eliminating the need for a separate die paddle or other die support aside from the leads 36 themselves.
The configuration of the '245 patent is said to assist in limiting the ingress of corrosive environmental contaminants to the active surface of the die, achieve a larger portion of the circuit path length encapsulated in the packaging material applied after wire bonding, and reduce electrical resistance caused by the bond wires 32 by placing the lead ends in closer proximity to the bond pads 34 (i.e., the longer the bond wire, the higher the resistance). Although this configuration offers certain advantages, it requires that bond wires 32 be individually attached between the bond pads 34 and the leads 36. Furthermore, bond wires exhibit an inherent problem called bond wire sweep. When encapsulating a bare die assembly, the die assembly is generally placed in a mold and a molten filled-polymer encasing material is injected under pressure into the mold. The molten encasing material then surrounds and encases the die assembly as it conforms to the mold cavity. Although encapsulation is an effective means for protecting a bare die assembly, the flow front of the encasing material employed in the process causes stresses on the bond wires. Since this molten material is viscous, it tends to place directional forces transversely to the direction of the bond wires as the encasing material is injected into the mold. Such directional forces cause the bond wires to deflect which can, in turn, cause the bond wires to short with adjacent bond wires or bond pads.
Furthermore, wirebonding also experiences problems with wire loop height which dictate semiconductor package thickness, as well as problems with heel breaks disconnecting the wire at a bond from the lead frame and/or bond pad. Further, as semiconductor dice become smaller, wirebonding requires more precise and expensive equipment to place and attach the bond wires.
U.S. Pat. No. 5,252,853 issued Oct. 12, 1993 to Michii ("the '853 patent") illustrates an LOC arrangement on a semiconductor die 40 which does not use bond wires. With reference to FIG. 6 herein, in such an arrangement the leads 42 are extended over the semiconductor die 40 toward centrally located bond pads 44 (shown in shadow). The leads 42 are held in position on the semiconductor die 40 by dielectric tape 46. The leads 42 extend to a position over their respective bond pads 44 wherein the leads 42 are bonded directly to their bond pads 44. Thus, the '853 patent eliminates bond wires and the problem associated therewith.
However, a fundamental limitation in present LOC/LUC semiconductor dice packages exists in the bond pad configurations. As illustrated in the '245 patent and the '853 patent, present LOC/LUC arrangements generally arrange the bond pads in rows along the center. Thus, as the semiconductor industry develops increasingly miniaturized components and greater packaging densities of integrated circuits, the bond pads and bond pad pitch (spacing) must also decrease in size. As the-size of the bond pads decreases, there is less area for lead or wire attachment. The reduction in attachment area requires expensive and more precise bonding equipment and results in an increased likelihood in bonding failures, both of which increase the cost of the semiconductor chip by increasing required capital invested or by lowering chip yields.
So-called "flip-chip" attachment techniques, commonly employing solder reflow or so-called "C4" (for Controlled Collapse Chip Connect) techniques to attach die bond pads to carrier substrate terminals, are also known in the art. The flip-chip bond pads are commonly configured in an array (rectangular, circular, etc.) or in multiple adjacent rows on a wider pitch (spacing) than is commonly employed with conventional, LOC or LUC die and lead frame assemblies. However, to the inventor's knowledge, a "flip-chip" attachment technique to electrically connect and physically secure a die to a lead frame has not been employed. Thus, the robust connections and wide or open bond pad pitch offered by flip-chip techniques have gone unrecognized in the context of lead frame-carried dice.
Therefore, it would be advantageous to develop a technique and a device which allow the semiconductor dice bond pads to maintain a relatively large size and pitch despite decreasing semiconductor size, while using commercially-available, widely-practiced semiconductor device fabrication techniques to arrange and form the bond pads and attach the lead fingers of a lead frame thereto.